Digital ASIC DFT test requirements—sample checklist
A companion checklist to "Successful ASIC test requires cooperation," which appeared in our December 2001 issue.
Paul Yohannes, Mint Technology, Fairport, NY -- Test & Measurement World, 12/1/2001 8:55:00 AM
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Digital ASIC DFT checklist (download a pdf version of the checklist) |
| 1) General |
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A) ASIC name: |
| B) Customer:
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| C) Brief description of ASIC:
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D) Technology/library (e.g., 0.18-mm CMOS/S11r2): |
| E) Principal (lead) design engineer:
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| F) Verification engineer:
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| G) DFT/test engineer:
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| H) Gate count (approx.):
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| I) Number of flip-flops (approx.):
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| J) Vendor-supplied hard or soft macros:
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| K) Customer-supplied hard or soft macros:
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L) Internal RAM (size(s) and number of instances): |
| M) ASIC package (QFP, flip-chip, etc.):
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2) Scheduling |
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A) Date RTL should be complete: |
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B) Date first gate-level netlist is expected: |
| C) Date tape-out to vendor is expected:
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| D) Date prototype arrival is expected:
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| E) Expected volume (k devices/year):
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F) Specific scheduling concerns/constraints: |
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3) ASIC operating conditions |
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A) Operating conditions (consumer/commercial/military): |
| B) Ambient temperature:
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C) Junction temperature: |
| D) Approximate worst-case power consumption:
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E) Power-calculation method: |
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F) Heat sink or cavity-down package required? (Y/N): Note: Cavity-down package will dissipate heat through contact with PCB. |
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4) I/O |
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A) Total I/O signal count: |
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B) Test I/O (JTAG, scan, etc.) included in total I/O |
| C) Number of inputs:
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D) Number of outputs: |
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E) Number of bidirectionals: |
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F) Number of pull ups: |
| G) Number of pull downs:
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| H) Number of VDD:
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| I) Number of VSS:
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| J) Total free package I/O available (unconnected): |
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5) Test methodology |
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A) Scan methodology (full/partial): |
| B) JTAG (IEEE 1149.1) (Y/N):
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C) Separate scan I/O pins used in JTAG designs (e.g., No scan through TAP)(Y/N): |
| D) Scan through TAP (Y/N):
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| E) Fault coverage requirements (%):
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| F) Internal RAMBIST (Y/N):
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| G) External RAM BIST (Y/N):
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H) Logic BIST (Y/N): |
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6) Clock(s) methodology/testability |
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A) Number of clock domains: |
| B) Clock-domain details:
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C) Clock-boundary synchronization methods (in order of preference):
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| D) Maximum clock frequency (scan vectors):
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E) Maximum clock frequency (functional vectors): |
| F) Gated or derived clocks:
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| G) Latches:
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| H) Reset strategy (single asynchronous reset recommended):
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| I) Soft or gated resets:
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| J) Asynchronous circuitry other than reset:
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7) Vector Formats and Considerations |
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A) Target tester: |
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B) Custom hardware (load board) required? (Y/N): |
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C) Multiple scan-chain capability of target tester (number of chains): |
| D) Total number of scan chains (proposed):
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E) Multiple scan chain limits (number of flops/chain): |
| F) Tester capabilities vs. scan chain requirements checked? (Y/N):
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G) Target tester high-Z capability: (Y/N): |
| H) IDDQ vectors required: (Y/N)
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| I) Vector format (serial scan vector set) (e.g., Verilog, WGL):
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| J) Vector format (parallel scan vector set) (e.g., Verilog, WGL):
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| K) Are multiple parallel (ATPG) vector sets acceptable? (Y/N): |
| L) Serial ATPG vector-count limit:
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| M) Parallel ATPG vector-count limit:
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| N) Functional vector-count limit:
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| O) Are multiple functional vector sets acceptable? (Y/N):
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| P) Additional charges for exceeding vector count limitations:
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| Q) Additional special testing required (e.g., voltage supply variation, extreme temperature tests):
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R) Additional charges for special testing: |
