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BIST does support Serdes test
January 17, 2007
In a guest commentary item posted here, Steve Sunter of LogicVision takes me to task for a December column in which I conflated Serdes with RF and other functions that aren’t particularly amenable to test using DFT techniques. He is correct that Serdes devices constitute a poor example in this case; I am well aware that LogicVision, for instance, has teamed up with GDA Technologies on Serdes test IP.
The point I should have and had wanted to make in the column was that I believe vendors will continue using expensive high-clock-rate ATE instruments for functions such as Serdes test, despite the availability of Serdes BIST tools—witness last May’s introduction by Verigy (then Agilent) of the Pin Scale HX high-speed extension card for its 93000 SOC Series tester, which supports characterization for devices and interfaces with serial data rates up to 12.8 Gbps. What will be interesting is to see how semiconductor companies choose to mix and match BIST and instrumentation approaches to their Serdes test operations at device-characterization and production-test stages. Will BIST complement or completely replace high-speed pin cards? Has anyone yet moved to an all-BIST approach for Serdes production test?
Posted by Rick Nelson on January 17, 2007 | Comments (0)
