Rick Nelson

ASML and IMEC: from planar transistors to 3D microthrusters
October 21, 2008

Two-dimensional semiconductor process technology has had a successful 50 year history since Gordon Moore designed the first commercial planar transistor. And there is no end in sight, as firms such as ASML continue to develop innovative photolithography equipment and research organizations like IMEC focus on sub-32-nm process technologies. Nevertheless, 3D semiconductor structures are emerging that serve a variety of application areas, and in fact older-generation 2D lithographic equipment can often be adapted to form 3D structures.

Presenters at research review meetings held last week at ASML in Veldhoven, the Netherlands, and at IMEC in Leuven, Belgium, discussed innovations in 2D and 3D technologies. For its part, ASML unveiled innovations in its TwinScan lithography platform. The new TwinScan NXT features a new light-weight planar wafer stage design that enables high acceleration to reduce positioning (stepping) times, thereby improving productivity by more than 30 percent, according to presenters, who added that the double patterning techniques that will serve the industry until EUV (extreme ultraviolet) techniques become commercially viable in 2010. Laura Peters, editor-in-chief of sibling publication Semiconductor International, has more on the TwinScan NXT.

IMEC presenters commented on the organization’s efforts to extend process technologies below 32 nm through the development of lithography, front-end, and back-end innovations—all of which are part of its “More Moore” initiative, according to Luc Van den hove, executive VP and COO at IMEC. The “More Moore” effort is complemented, he said, by the “More than Moore” initiative, which aims at the heterogeneous integration of MEMS devices, RF and mixed-signal devices, nanophotonics, and organic electronics using advance packaging technologies.

One IMEC initiative that might be said to bridge the gap between the “More Moore” effort and the “More than Moore” initiative is the move toward 3D integration. I describe the 3D integration effort in more detail in “IMEC demonstrates 3D stacked integrated circuits.” Essentially, the integration involves the interconnection of stacked planar dies by means of copper through-silicon vias. In his presentation, Van den hove placed 3D integration in the “More Moore” category as a way of increasing device complexity and density.

But not all innovations necessarily involve increasing device density. Jos Vreeker, technology specialist, corporate communications, at ASML, said during his research review presentation that lithography is at the heart of many high-growth applications we take for granted every day. These applications, he said, are very high tech, but in a different form of high tech than the one we envision when considering Moore’s law. The devices that serve such applications, he said, are often built in 200-mm wafer fabs using older generation equipment. Specific examples, he said, include micro mirrors for projectors, DNA analyzers, pressure sensors, camera pills with image sensors, ink-jet heads, disk-drive thin-film heads, labs-on-chips for blood analysis, gyroscopes (such as the one used in the iPhone), and energy harvesters. Companies making such devices, he said, include HP, ST Microelectronics, TI, Robert Bosch, TSMC, Seagate Technologies, Hitachi Global Storage Technologies, Fujitsu, and TDK Group.

Also speaking at the ASML research review meeting, Henk van Zeijl of DIMES/Delft University of Technology described some more unusual applications. In a presentation titled “From 2-D lithography to 3-D structures: An escape from “flatland,” he described a micro sieve, intelligent nozzles, integrated micro grippers, and micro reaction chambers—all formed by extruding 2D-like photoresist patterns into the third dimension using anisotropic etching.

He noted that the 3-D concept was not new in electronics—vacuum tubes and early transistors were, in fact, 3-D devices. But now, he said, 2-D lithography can be adapted to form 3-D structures such as an integrated spectrometer. The 2-D techniques, he said, can be used to create 3-D-like photoresist patterns that can be used, for example, to form trough-silicon vias and vertical electrodes on cavity sidewalls. Gray-scale lithography, he said, can be used to form arbitrary profiles.

He concluded by noting that mainstream lithography is optimized for 2D pattern transfer for high-volume IC fabrication. But when combined with the wide range of etching techniques now available—ranging from wet chemical isotropic etching to highly anisotropic DRIE (deep reactive ion etching)—2D lithography can allow us to fabricate a wide range of 3D structures—such as thrusters for Delft’s Delfi Cube C3 nanosatellite.

Posted by Rick Nelson on October 21, 2008 | Comments (0)