Rick Nelson

ITC panel to address yield learning: who pays, who gets the data
October 7, 2008

Conventional wisdom holds that the foundry owns the responsibility to fund and manage the tools and processes associated with semiconductor product quality, says Phil Burlison at Verigy. However, he says, in the newer technology nodes, yield accountability involves more than the optical inline inspection and other related monitoring functions that are an integral part of the wafer-fabrication process. As process geometries shrink, he says, “There is a growing view that the quantitative data generated on ATE can be used well beyond a ‘go/no go’ filter for defects. Integral to this new process are the tools that can analyze and convert test-failure data into meaningful indicators of design/process problems.”

The emergence of such tools poses questions: who pays for them, how is the data that the tools generate promulgated, and to whom? To investigate those questions, Burlison has organized an International Test Conference panel discussion titled “Yield Learning¯Who Gains, Who Picks Up the Tab?”

Says Burlison by way of background, “Since it is generally the semiconductor product group that directly or indirectly owns test—and directly or indirectly pays for it—that group becomes the most likely candidate to pick up the new tab for ‘yield learning.’ But if the resulting test information indicates problem areas that the foundry must respond to, how is this efficiently fed back in a timely manner?”

To discuss such issues, Burlison has recruited several panelists, including Carlos Aguilar of Qualcomm, who will present the semiconductor company point-of-view; Debbora Ahlgren of Verigy, who will provide a tester-company perspective; and Bill Miller of IBM, who will discuss foundry considerations.

Burlison hopes first that the panelists can begin by agreeing that yield learning is necessary and valuable. He then expects them to address questions of cost and data allocation as well as questions of responsibility when yield problems are attributable to the interaction of product design and fabrication-process variability.

I’ll be serving as panel moderator. If you’ve got questions you would like to ask the panelists, let me know before the event, scheduled for Wednesday October 29 from 4:15 p.m. to 5:45 p.m.

The ITC and associated Test Week activities will be held October 26-31 in Santa Clara, CA. Read my interview with program chair Nur Touba, "Power-aware test hot at ITC, as is analog test."

Posted by Rick Nelson on October 7, 2008 | Comments (0)